The present invention relates to a retiming circuit for pulse signals, exchanged between a transmitter device (typically a microprocessor) and a receiving device (typically a peripheral). In particular, the circuit is intended to be built-in into a peripheral produced with integrated technology.
To interface the microprocessors with the outer environment, the use is known of asynchronous communication circuits, employed as peripherals having the task of receiving pulse signals from the outer environment, arriving at arbitrary times, and synchronizing said asynchronous signals with the microprocessor, i.e. recovering them so as to feed them to the microprocessor as pulses strictly correlated to the clock waveform edges of the microprocessor itself. The asynchronous communication circuit is generally also assigned to the task of transferring synchronous signals produced by the microprocessor towards the asynchronous outer environment.
In other cases, the signals generated by the microprocessor must be fed to a synchronous communications line, or to another microprocessor, and therefore must be provided with a synchronism of their own, which however differs from the one of the transmitting microprocessor. For this purpose, communication circuits or interfaces of the synchronous type are used, and thus it becomes necessary to make a distinction between different clocks, i.e. between the clock of the microprocessor, or main clock, and the local clock of the circuit or transfer gate.
Naturally, the pulse signals to which reference is made may be composed not only of a single line, but even, and indeed most often, of groups of signals in parallel, e.g. of an octet of lines which at each transfer supply one byte of information, and which all together constitute the event to be retimed. Obviously, the same retiming circuit or gate can simultaneously process in parallel all the signals of the group.
In performing their timing or retiming function, the interface circuits must naturally ensure the correct recognition of the signals, i.e. they must avoid both the inadvertent skipping of an event and the reading of the same event two or more times (thus generating nonexistent signals). Such situations could occur, e.g., in the absence of appropriate circuital provisions, in the first case due to a read-out with an excessively low frequency, and in the second in the case of a read-out with an excessively high frequency.
In order to solve the above described problems, up to now retiming gates have been used which require several phases of the clock to complete the process of recognizing and regenerating an event and to be again ready to receive a new event. Furthermore, known synchronizing gates, in order to operate correctly, must operate in synchronism with the main clock. Finally, known gates are generally based on analog operating concepts, and this can some times lead to problems of implementation in otherwise fully digital circuits.